Analog Circuit Design: High-Speed A-D Converters, Automotive by Arthur H.M. van Roermund, Herman Casier, Michiel Steyaert

By Arthur H.M. van Roermund, Herman Casier, Michiel Steyaert

Analog Circuit layout includes in overall 18 tutorials. They mirror the contributions of 6 specialists in all the 3 fields lined by means of the 3 chapters pointed out within the subtitle, as offered on the fifteenth workshop on Advances in Analog Circuit layout (AACD) held in Maastricht, April 2006.

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Extra info for Analog Circuit Design: High-Speed A-D Converters, Automotive Electronics and Ultra-Low Power Wireless

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6. 20-GSa/s ADC Multi-chip Module Photo. K. Poulton et al. 28 Fig. 7. ADC Effective Bits and Gain vs. Input Frequncy. 8. Power The power breakdown of the two chips is shown in Table 1. The core ADC slices were chosen for power efficiency and provided good FOM values for their process generation. However, the overall power FOM of the chips is around 10 times worse. This is due to several factors. On the analog side, the interleaved clock generator increases the power by about 150 mW. The power required for the full-speed outputs or on-chip memory nearly doubles the chip power.

A key advantage of this architecture is that the two-step approach allows for an area and power efficient design. Additionally, it can use simple differential-pair amplifiers, which are very well fit for low-voltage operation. The basic architecture of the two-step subranging ADC, comprising a coarse ADC (CADC) and a fine ADC (FADC), is explained in Sec. 2. Sec. 3 discusses one of the key elements in this design, the voltage subtractor. The timing of this subranging ADC is explained in Sec. 4. Techniques that are used to obtain a low-power and low-area ADC are discussed in Sec.

Huijsing, Rudy J. C. Sansen “Analog Circuit Design”, Kluwer Academic Publishers, December 1992, ISBN 0-7923-9288-4. 35-um CMOS”, IEEE International Solid State Circuits Conference Digest of Technical Papers, pp. 166-167, Feb 2002. 18-um CMOS”, IEEE International Solid State Circuits Conference Digest of Technical Papers, pp. 318-319, Feb 2003. 25GS/s 4b ADC in a 90nm Digital CMOS Process”, IEEE International Solid State Circuits Conference Digest of Technical Papers, pp. 566-567, Feb 2006. 2V 6b 1GS/s Two-Step Subranging ADC”, IEEE International Solid State Circuits Conference Digest of Technical Papers, pp.

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