CMOS Single Chip Fast Frequency Hopping Synthesizers for by Taoufik Bourdi

By Taoufik Bourdi

During this publication, the authors define exact layout technique for quick frequency hopping synthesizers for RF and instant communications functions. there's nice emphasis on fractional-N delta-sigma dependent section locked loops from necessities, approach research and structure making plans to circuit layout and silicon implementation. The built innovations within the e-book may also help in designing very low noise, excessive pace fractional-N frequency synthesizers.

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Extra info for CMOS Single Chip Fast Frequency Hopping Synthesizers for Wireless Multi-Gigahertz Applications: Design Methodology, Analysis, and Implementation (Analog Circuits and Signal Processing)

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Gain terms and their units, as well as phase noise and their units are included (Table 3-3). From basic control theory, it is easy to determine the transfer 28 Chapter 3 function of the individual noise contributors. Those are given in the following equations. 18) The output noise power is the product of the input noise power and the magnitude squared of the transfer function. The total output noise power is calculated by summing the output noise power contributed from each noise source (assuming the noise sources are uncorrelated).

The PFD model gives a duty cycle output that can take values in the range of í1 to +1. When the duty cycle is negative there is discharge to the loop filter and when the duty cycle is positive there is a charge to the loop filter. 48 Chapter 4 Figure 4-3. PFD/CP Characteristics Showing the Dead-Zone Region System Simulation of '6 -Based Fractional-N Synthesizers 49 The PFD/CP linearity curve, whether taking into account the deadzone or not, is provided by a lookup table immediately after the PFD.

That results in the usage of fractional division ratio to satisfy the output VCO frequency and frequency step of interest. Frequency synthesizers employing such fractional dividers are called fractional-N frequency synthesizers. Figure 3-14 shows a conventional fractional-N frequency synthesizer. Early Implementation of the fractional dividers employs a digital accumulator [12] that controls a dual-modulus divider. The synthesizer shown in Figure 3-14 is termed first-order fractional-N frequency synthesizer.

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